Once you understand the philosophy of the demo, you
can also:
See our Test
Functions page for a quick introduction
to the Pinter functions and reference material discussing
their value for testing optimization solvers.
Go to our Demo
Interface page to submit your very own
problem to the demo server.
Questions should be directed to:
demo overview
Accelogic’s reconfigurable computing algorithms have been successfully demonstrated for the global optimization of
the family of Pinter functions in one dimension.
Through this demo server, you can submit your own optimization
problems to the same exact prototype used by Accelogic for
its original feasibility study.
The figure below illustrates what happens “behind the
scenes” every time a user submits a problem to the demo
interface. As you will see from the results, when programmed
with Accelogic’s reconfigurable computing algorithms, the FPGA
board is both more accurate and faster than a 1,000-node PC
cluster programmed with a state-of-the-art parallel branch &
bound algorithm. As you can see from the cost of the hardware
(a Dell D-1100 PC and a Xilinx Virtex-II MM general purpose
development board), Accelogic’s solution is also two
orders of magnitude less expensive.
