Sep 1, 2010

Accelogic's Fusion/HEP program gains momentum.

The recent set-aside of funds from the U.S. Department of Energy, NASA, and the U.S. Department of Defense to work on the acceleration of Fusion/HEP applications, opens the search for new Strategic Project Partners which will be selected for close collaboration with the primary goal of "pushing the envelope on the development of Fusion Energy and/or HEP science".

Jul 29, 2010

Accelogic's Sca/LAPACKrc surpasses 1,000x for large-scale sparse linear algebra.

The recent advances in the Sca/LAPACKrc research program -through innovative hybrid CPU/GPU/FPGA methods- have delivered a stunning 1,000x acceleration over today's fastest processor core for the solution of large-scale sparse matrices. This is the first-of-its-kind achievement in heterogeneous supercomputing.

Jul 26, 2010

Accelogic expands in the cloud.

Following Accelogic's dynamic 8 month intellectual property initiative on "CPU/GPU/FPGA algorithms for the cloud", the company now seeks Strategic Project Partners that can benefit from the acceleration enabled by the LAPACKrc program. In team with Project Partners, Accelogic will complete the creation of novel numerical libraries to provide next-generation speed/efficiency to existing cloud systems.

Jun 28, 2010

Accelogic launches Fusion/HEP program.

Accelogic, a leader in pioneering breakthrough CPU/GPU/FPGA algorithms for solving large-scale linear equation systems, launches an agressive technology development program aimed at accelerating the fundamental computational bottlenecks in Fusion Energy and High-Energy Physics research.

Jun 4, 2010

Accelogic receives NASA Best Technology Award for the second time in three years.

Accelogic has received the NASBO award (for Best Technology 2010). This award, developed by the Southeast NASBO Chapter, encourages and supports commercialization of NASA technologies developed by Accelogic.

Apr 29, 2010

The Department of Energy grants award for enhancing the LAPACKrc library with extreme-speed FFT solvers.

Accelogic is awarded a contract by the Department of Energy to expand the scope of the Sca/LAPACKrc package. This development targets novel hybrid CPU/GPU/FPGA algorithms for heterogeneous and CPU-based supercomputers, which will render unprecedented acceleration and scalability for computing the Fast Fourier Transform -a computational kernel of paramount importance in science and engineering.

Apr 22, 2010

Accelogic demonstrates more than 120x speedups for the Direct Sparse Solvers.

Accelogic's Direct Sparse solver prototype, which is part of the already successful Sca/LAPACKrc library, achieves a revolutionary 120x speedup for solving direct sparse equation problems arising from multiple disciplines, such as CFD, structural analysis, electromagnetics, heat transfer, robotics, and semiconductor devices, among many others. The technology consumes at least two orders of magnitude less energy per Gflop, thus paving the road towards energy-efficient "green" computing and the realization of feasible exa-scale computing.

Nov 26, 2009

Accelogic in the cloud.

Accelogic expands the scope of the already successful development program on the utmost acceleration of large-scale linear equations to cloud computing. With a vigorous initiative on enabling the "HPC in the cloud" dream through the use of its breakthrough CPU/GPU/FPGA algorithms, Accelogic predicts accelerations of up to 1,000x in scientific applications when connected to a cloud infrastructure, at minimal economic cost.

Sep 21, 2009

Accelogic submits its 15th patent application.

Accelogic consolidates its leadership in breakthrough heterogeneous algorithms for HPC and escalates its intellectual property capital with its 15th patent submission.

Apr 17, 2009

Accelogic demonstrates over 90x speedup for the Least Squares solver component of LAPACKrc.

Accelogic's Least Squares solver prototype, consolidates Accelogic and the Sca/LAPACKrc library as world leaders in breakthrough computing algorithms for accelerating large-scale linear algebra systems. The prototype has achieved more than 90x acceleration for solving large-scale least squares problems, which offers a direct benefit to numerous science and engineering applications.

Nov 5, 2008

Accelogic receives NASA Best Technology Award.

Accelogic received the NASBO award, developed by the Southeast NASBO Chapter to provide grants and mentoring opportunities to NASA SBIR companies located in the Southeast. The purpose of these grants is to encourage and support commercialization of NASA SBIR technologies.

Sep 25, 2008

Accelogic receives Grand Prize Award from the South Florida Technology Alliance (SFTA).

Accelogic was selected by the SFTA (South Florida Technology Alliance) as one of the most promising emerging companies in South Florida. Dr. Juan Gonzalez, Accelogic's President, received this award from Chip Casanave, SFTA President and CEO of Miami's Data Access Worldwide, at the SFTA At-Large Meeting. The South Florida Technology Alliance (SFTA) promotes the growth, success and awareness of the regional technology community.

May 5, 2008

U.S. Department of Energy awards Accelogic's LAPACKrc extended contract.

The U.S. Department of Energy has awarded Accelogic a contract to continue extending its Sca/LAPACKrc package. This development is targeted to extremely fast least-squares algorithms for heterogeneous supercomputers comprised of standard CPUs and off-the-shelf FPGA-based reconfigurable processors.

March 15, 2008

Accelogic demonstrates 150x speedup for sparse solver component of LAPACKrc.

Accelogic has demonstrated more than 150x speedup in solving sparse linear equation problems across multiple disciplines. Accelogic’s LAPACKrc technology utilizes reconfigurable computing hardware integrated with a standard processors. Speedups of more than 150x for benchmark problems in computational electromagnetics, computational fluid dynamics, structural analysis, and heat transfer are proven.

February 28, 2008

Accelogic submits its 10th patent application.

Accelogic, a leader in pioneering breakthrough computing algorithms for solving large-scale linear equation systems, continues to expand its patent portfolio. With 10 patents now filed, Accelogic’s innovations are increasingly protected.

June 20, 2007

Accelogic and Stanford University join forces to enhance LAPACKrc performance.

Accelogic and Stanford University were awarded a U.S. Air Force contract to deploy new sparse iterative solvers that are orders of magnitude faster than today’s solvers. The new algorithms utilize hybrid CPU/FPGA reconfigurable computing elements enabled by new mathematical theories pioneered by Accelogic's Science Board.

May 1, 2007

U.S. Department of Energy joins LAPACKrc effort.

The U.S. Department of Energy has funded Accelogic to deploy its LAPACKrc core technology for accelerating the solution of large-scale linear equations. LAPACKrc is anticipated to provide 2 to 3 orders of magnitude acceleration in solving large-scale linear equations.

March 13, 2007

NASA embraces demo of Accelogic's leading product: LAPACKrc.

Accelogic has demonstrated its breakthrough LAPACKrc algorithms for fast linear equation solutions at NASA Ames. The LAPACKrc reconfigurable computing software was run on a single FPGA chip demonstrating the speed equivalent of a 240-processor supercomputer for a subclass of the NASA “NAS benchmarks” program.

Dec 10, 2006

Accelogic delivers world’s fastest linear equation solver to U.S. Air Force.

Accelogic successfully demonstrated more than 50x speedup in solving linear equation problems versus a standard commodity processor. The solver is now delivered to Wright-Patterson Air Force Base, where it will undergo further evaluation and testing.

Nov 14, 2006

NASA selects Accelogic to deploy hybrid CPU/FPGA supercomputing pilot program.

This NASA contract initiated to demonstrate sustained supercomputing performance for large-scale CFD simulation codes exploiting novel CPU/FPGA collaborative algorithms recently discovered by Accelogic's numerical methods team.

July 12-14, 2006

Accelogic pioneers industrial training series on High Performance Computing.

In order to expand penetration of current reconfigurable computing, Accelogic has created the short course, “Algorithm Design in the Era of Reconfigurable Computing.” Held in Dayton, the course had over 30 attendees from industry and academia, with application interests spanning aerospace, computational finance, radar engineering, video processing, and structural analysis.

May 20, 2006

Accelogic secures key contract from the Air Force Air Vehicles Directorate.

This R&D contract will quicken Accelogic’s demonstration of its unique FPGA-accelerated algorithms for large-scale numerical linear algebra and structural analysis.

May 18, 2006

Accelogic presents at MDOC’2006 (Multidisciplinary Design Optimization Conference), Gottingen, Germany.

The talk, Very Fast Hardware-Based Global Search Methods for MDO, described an enabling technology for aerospace design: massively concurrent algorithms exploiting the emerging field of reconfigurable computing. The promise is to deploy MDO algorithms that are 2 to 5 orders of magnitude faster than today’s state of the art, using hybrid CPU/FPGA computing.

Mar 7, 2006

Accelogic exhibits at the 31st AIAA Dayton-Cincinnati Aerospace Sciences Symposium.
Accelogic exhibited an interactive demo illustrating the unprecedented speed and capacity of its optimization technology, and presented the new opportunities this technology opens for the discovery of groundbreaking supersonic-plane designs.
 
 
Oct 7, 2005
 
Accelogic demonstrates the world’s first reconfigurable computing algorithms to achieve greater than 1,000x speedups for numerical optimization applications.
The world’s first prototype of a massively parallel reconfigurable computing algorithm demonstrating greater than 1,000x speedups for global optimization has been successfully implemented and benchmarked today. Preliminary results using the Pintér benchmarking functions indicate that when implemented in a commercial reconfigurable computing system, the new algorithm outperforms (in both speed and accuracy) a 1,000 processor supercomputer programmed with a state-of-the-art parallel branch-and-bound algorithm. Accelogic’s solution is also two orders of magnitude less expensive.
 
 
May 15, 2005
 
Accelogic secures seed funding from the U.S. Department of Defense.
Accelogic’s mission: to revolutionize the field of numerical computing through affordable reconfigurable-computing algorithms that reduce execution times from weeks to seconds.